1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a channel stop structure of a power device and a method of manufacturing the channel stop structure.
2. Description of the Background Art
In a peripheral region of a chip in which a power device such as a power MOSFET or an insulated gate type bipolar transistor is formed, there is formed a channel stop structure for preventing a depletion layer extended from a main junction from being provided over the peripheral region of the chip in order to maintain a breakdown voltage of a semiconductor device. By recent investigations, it has turned out that the channel stop structure is important to stabilize the breakdown voltage of the semiconductor device.
FIG. 26 is a sectional view showing a first conventional channel stop structure. An N+-type impurity implantation region 152 in which an impurity such as phosphorus or arsenic is implanted in a high concentration is formed in an upper surface of an N−-type silicon substrate 150 in the vicinity of an edge 151 (a peripheral portion) of a chip.
FIG. 27 is a sectional view showing a second conventional channel stop structure. A silicon oxide film 153 is formed on an upper surface of an N−-type silicon substrate 150 excluding a peripheral portion of a chip. An N+-type impurity implantation region 152 is formed in an upper surface 154 of the N−-type silicon substrate 150 in a portion exposed from the silicon oxide film 153. An aluminum electrode 155 is formed on the upper surface 154 of the N−-type silicon substrate 150. The aluminum electrode 155 is extended over the silicon oxide film 153 to constitute a field plate. Such a channel stop structure is employed in a semiconductor device in which a planer type bipolar transistor is formed, for example.
FIG. 28 is a sectional view showing a third conventional channel stop structure. A silicon oxide film 156 is formed on an upper surface of an N−-type silicon substrate 150 excluding a peripheral portion of a chip. An N+-type impurity implantation region 152 is formed in an upper surface 157 of the N−-type silicon substrate 150 in a portion exposed from the silicon oxide film 156. A polysilicon film 158 is formed on the upper surface 157 of the N−-type silicon substrate 150. The polysilicon film 158 is extended over the silicon oxide film 156 to constitute a first field plate. A part (the most peripheral portion) of the upper surface 157 of the N−-type silicon substrate 150 is exposed from the polysilicon film 158.
Moreover, a silicon oxide film 159 is provided on the polysilicon film 158 in a portion formed on the silicon oxide film 156 and on the silicon oxide film 156 in a portion where the polysilicon film 158 is not formed. An aluminum electrode 160 is formed on the most peripheral portion of the upper surface 157 of the N−-type silicon substrate 150. The aluminum electrode 160 is also provided in contact with the polysilicon film 158, and furthermore, is extended over the silicon oxide film 159 to constitute a second field plate. A channel stop structure having such a double field plate is employed in a semiconductor device in which a planer type MOSFET having a gate electrode formed of polysilicon is provided, for example.
FIG. 29 is a sectional view showing a fourth conventional channel stop structure. A silicon oxide film 161 is formed on an upper surface of an N−-type silicon substrate 150 excluding a peripheral portion of a chip. An end on the edge 151 side of the silicon oxide film 161 has a small thickness. An N+-type impurity implantation region 152 is formed in an upper surface 162 of the N−-type silicon substrate 150 in a portion exposed from the silicon oxide film 161. A polysilicon film 163 is formed on the upper surface 162 of the N−-type silicon substrate 150. The polysilicon film 163 is extended over the silicon oxide film 161 to constitute a first stepped field plate. The most peripheral portion of the upper surface 162 of the N−-type silicon substrate 150 is exposed from the polysilicon film 163.
Moreover, a silicon oxide film 164 is formed on the polysilicon film 163 in a portion formed on the silicon oxide film 161 and on the silicon oxide film 161 in a portion where the polysilicon film 163 is not formed. An aluminum electrode 165 is formed on the most peripheral portion of the upper surface 162 of the N−-type silicon substrate 150. The aluminum electrode 165 is also provided in contact with the polysilicon film 163, and furthermore, is extended over the silicon oxide film 164 to constitute a second field plate. In a semiconductor device in which a planer type MOSFET having a gate electrode formed of polysilicon is provided, recently, a channel stop structure having the double field plate shown in FIG. 29 has been employed.
FIG. 30 is a sectional view showing a fifth conventional channel stop structure (see Japanese Patent Application Laid-Open No. 8-264787 (1996)). A P−-type epitaxial layer 201 is formed on a P+-type substrate 200. A field oxide film 205 is formed on an upper surface of the P−-type epitaxial layer 201 excluding an edge 202 portion of a chip. A P-type diffusion layer 207 is formed in the upper surface of the P−-type epitaxial layer 201 in a portion exposed from the field oxide film 205.
A deeper trench 203 than the P-type diffusion layer 207 is formed in the upper surface of the P−-type epitaxial layer 201 in a portion where the P-type diffusion layer 207 is provided. An insulating layer 204 having a smaller thickness than that of the field oxide film 205 and formed of oxide is provided on an inner wall of the trench 203 and on the upper surface of the P−-type epitaxial layer 201 in a portion exposed from the field oxide film 205. Moreover, a doped polysilicon film 208 is formed to fill in the trench 203 provided with the insulating layer 204 and to be extended over the field oxide film 205 to constitute a field plate. Moreover, a BPSG layer 206 is formed to cover the doped polysilicon film 208 and the field oxide film 205.
In the publication described above, such a channel stop structure has been employed for a semiconductor device provided with a transistor having a trench formed in the upper surface of the P−-type epitaxial layer 201 in an active portion, a gate oxide film formed on an inner wall of the trench, and a gate electrode formed of doped polysilicon provided to fill in the trench (that is, a trench type insulated gate).
The above-mentioned publication has described a problem of “channeling” in a P-channel type MOSFET. More specifically, there have been described “channeling depends on a quantity of fixed electric charges in an oxide film and in an upper surface portion of a substrate provided thereunder. The fixed electric charges of this kind are depleted at an oxidizing step. However, the depletion enables inversion (channeling) to be carried out.” “This is caused by separation of boron from a main surface of the substrate at the oxidizing step and P-type electric charges in the main surface of the substrate are decreased due to the boron.” and “It has been found that the boron to be a dopant becomes a problem.”
As a solution of the channeling, the structure of FIG. 30 has been shown. There has been described that a thickness of the insulating layer 204 is made smaller than that of the field oxide film 205 and depletion of the boron from an upper portion of the P−-type epitaxial layer 201 to the insulating layer 204 is thereby made less than depletion to the field oxide film 205, resulting in suppression of the channeling.
However, the first to fourth conventional channel stop structures insufficiently produce the effect of preventing the depletion layer extended from the main junction from being formed over the peripheral region of the chip. As a result, there is a problem in that the effect of stabilizing the breakdown voltage of the semiconductor device is insufficient.
Referring to the fifth conventional channel stop structure, moreover, the above-mentioned publication has described only the case in which the P-type diffusion layer 207 is formed in the P−-type epitaxial layer 201. Therefore, there is a problem in that whether or not the same effects can be obtained is unknown if an N-type diffusion layer is formed in an N-type silicon substrate (including an N-type epitaxial layer). Differently from the P type, particularly, an N-type impurity is segregated into a surface of a silicon substrate at the oxidizing step in the case of the N type. Therefore, the channeling at the oxidizing step is not conceivable.